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Features
* Single-chip Sound Studio with Typical Applications including:
- Wavetable Synthesis, Serial MIDI In & Out, MPU-401 (UART) - Game-compatible Synthesis with Adlib Interface - Effects: Reverb and Chorus - DirectsoundTM, Direct3DsoundTM Accelerator with Static Buffer Support - Interactive 3-D Positioning - Four-channel Surround - Four-band Equalizer - Mixer High-quality Wavetable Synthesis - 16-bit Samples with up to 48 kHz Sampling Rate - Internal Computations on 28 Bits, DAC Support up to 20 Bits - Alternate Loop, 24 dB Digital Filter for Each Voice Professional Effects - 13 Delay Lines for Resonance-free Stereo Reverb Four-band Final Equalizer Allows Dramatic Sound presence Improvement Expandable - Minimum System: SAM9707 + 512K Bytes of ROM + 32K x 8 RAM + DAC - Maximum System: SAM9707 + 64M Bytes of DRAM + Codec + DAC High Performance - RISC Structure for Sound Synthesis/Processing - CISC Structure for Host Communication and Housekeeping - Audio Transfer at Maximum 16-bit ISA Bus Speed - Audio Transfer in Burst Mode: Removes DMA-controlled Transfer Burden Fully Programmable - Firmware Downloaded to Memory at Power-up. Easy Software Upgrade. - Chip Programming Open to Third-party Software Companies - Powerful Programming and Debugging Tools: Algorithm Compiler, Sound Editor, Assembler and Source Debugger. Direct Development from PC Environment, No Special Emulator Required Top Technology - Single Low-frequency Crystal Operation and Built-in PLL Minimize RFI - 144-lead TQFP Space-saving Package Pin and Function Compatible with SAM9407 with Additional Features for Professional Use: - Up to Eight Channels of Audio-in - Improved Digital Mix Levels and Digital Overflow Handling - Improved Tuning Accuracy - Additional DSP Micro-instructions and Datapath for More Efficient Audio Processing Algorithm Coding Pin-to-pin replacement for SAM9407 requires 3.3V core supply VC3.
*
Integrated Sound Studio SAM9707
* * * *
*
* *
Note:
Description
The SAM9707 is a highly integrated sound processor studio that combines a specialized high-performance RISC-based digital signal processor (synthesis/DSP) and a general-purpose 16-bit CISC-based control processor on a single chip. An on-chip memory management unit (MMU) allows the synthesis/DSP and the control processor to share external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the ISA PC bus, the on-chip MIDI UART and the codec control interface, with minimum intervention from the control processor.
Rev. 1711A-12/00
1
Pinout
Figure 1. SAM9707 in 144-lead TQFP Package
WD12 D15 WD11 D14 WD10 S1 WD9 WD8 S0 VCC CS GND WD7 WD6 WD5 WD4 WD3 I/O READY WD2 WD1 WD0 WA24 WA23 SBHE GND GND VCC WA22 RAS CAS WA21 WA20 D13 VC13 D12 WA19 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VCC IRQ GND I/O CS16 WD13 MIDI OUT WD14 DRA0 DRA1 WD15 GND VCC GND VC3 VC3 LFT X2 X1 RESET PDWN VCC GND DRA2 CRA3 MIDI IN RUN DRA4 VC3 GND VCC GND D0 CLBD VC3 D1 RBS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
GND D11 VCC D10 WA18 WA17 A2 A1 GND RD VCC WR WA16 WA15 WA14 WA13 WA12 WA11 WA10 A0 WA9 WA8 WA7 GND D9 VCC D8 WA6 WA5 WA4 WA3 GND D7 VCC D6 WA2
2
BOOT D2 VCC D3 GND DRA5 DAAD DRA6 DABD0 DRA7 DRA8 DABD1 WSBD WWE WCS0 WCS1 WOE VCC DRA9 GND P0 P1 P2 P3 TEST0 TEST1 TEST2 GND DRA10 WA0 DRA11 VCC D4 GND D5 WA1
SAM9707
SAM9707
Pin Description
Table 1. Pins by Function
Pin Name GND VC3 VCC D0 - D15 Pin Count 17 3 15 16 Type PWR PWR PWR I/O Function Power ground - All GND pins should be returned to digital ground. Core power +3.3V nominal (3V to 4.5V). All VC3 pins should be returned to +3.3V. Power +3V to +5.5V - All VCC pins should be returned to +5V (or 3.3V in case of single 3.3V supply). 16-bit data bus to host processor. Has enough driving power to drive ISA PC bus directly (24 mA buffer). Information on these pins is: - parallel MIDI (MPU-401 type applications) - Adlib control (game sound-type emulation) - Down-/upload of PCM data or application programs Direct ISA PC bus drive requires 5V VCC. Chip select from host, active low Write from host, active low Read from host, active low Selects one of eight internal registers - 0, 1: MPU-401 registers - 2, 3: 16-bit data (burst DMA mode) - 4-7: game sound registers Tri-state output pin. Can be connected directly to host IRQ line (24 mA). Bus high enable signal, active low. Normally connected to GND. Open drain output buffer (24 mA); driven low during 16-bit burst mode transfers to synchronize PC to the SAM9707 memory. Open drain output buffer (24 mA); driven low during 16-bit burst mode transfers. Indicates to host that a 16-bit I/O is in progress. Master reset input, active low. Schmitt trigger input. Crystal connection. Crystal frequency should be fSx256 (typ 11.2896 MHz). Crystal frequency is internally multiplied by four to provide the IC master clock. X1 can also be used as external clock input (3.3V input). X2 CANNOT BE USED TO DRIVE EXTERNAL CIRCUITRY. OUT Two stereo serial audio data outputs (four audio channels). Each output holds 64 bits (2 x 32) of serial data per frame. Audio data has precision of up to 20 bits. DABD0 can hold additional control data (mute, A/D gain, D/A gain, etc.). Audio data bit clock; provides timing to DABD061. Audio data word select. The timing of WSBD can be selected to be I2S or Japanese compatible. Stereo serial audio data input Serial MIDI IN input Serial MIDI OUT output
CS WR RD A0 - A1
1 1 1 3
IN IN IN IN
IRQ SBHE I/O READY I/O CS16
1 1 1 1
TSout IN OUT OUT
RESET X1, X2
1 2
IN
DABD0 - 1
2
CLBD WSBD DAAD MIDI IN MIDI OUT
1 1 1 1 1
OUT OUT IN IN OUT
3
Table 1. Pins by Function (Continued)
Pin Name WA0 - 24 WD0 - 15 RBS Pin Count 25 16 1 Type OUT I/O OUT Function External memory address (ROM/SRAM). Up to 32M words (64M 8-bit samples). PCM ROM/SRAM/DRAM data SRAM byte select: Should be connected to the lower RAM address when 8bit wide SRAM is used. The type of RAM (16 bits/8 bits) can be selected by program. PCM ROM chip select, active low. SRAM chip select, active low. SRAM/DRAM write enable, active low. Timing compatible with SIMM DRAM early write feature. PCM ROM/SRAM output enable, active low. Active high, specifies that built-in CPU bootstrap should be used at power-up (case of DRAM connection only). Multiplex DRAM address: 9-, 10-, 11-, 12-bit multiplex addressing can be used (from 256K x 16- to 16M x 16-type configurations). DRAM row address strobe DRAM column address strobe General-purpose configurable I/O pins. P1 to P3 can be configured as three additional stereo serial audio data inputs, providing the DAAD with up to eight channels of audio-in. Indicates type of external memory cycle. S1S0 = 01: Idle or refresh, 00: Synthesis access, 10: Instruction fetch, 11: Processor read/write High when the synthesis is initialized. Can be used as RESET for an external device (CODEC). PLL low pass filter. Should be connected to an external RC network test pin; should be returned to GND. Test pins; should be returned to GND. Power-down, active low.
WCS0 WCS1 WWE WOE BOOT DRA0 - 11 RAS CAS P0 - P3
1 1 1 1 1 12 1 1 4
OUT OUT OUT OUT IN OUT OUT OUT I/O
S0 - S1
2
OUT
RUN LFT TEST0 - 2 PDWN
1 1 3 1
OUT ANA IN IN
4
SAM9707
SAM9707
Typical Designs
Figure 2. Lowest Cost Design Architecture
ROM 256K x 16
SAM9707
SRAM 32K x 8
CODEC
or
- General MIDI-compliant Wavetable Synthesis - Compatible Reverb + Chorus - Wave Play and Record (One Stereo Channel) - Game-compatible Synthesis - 3-D Effect - Four-band Equalizer
DRAM 256K x 16
SAM9707
CODEC
Figure 3. Typical Design Architecture
DRAM 1M x 16 - Professional-quality General MIDI-compliant Synthesis - Sound Extensions - Additional Top-quality Drumsets and Bass - Compatible Reverb + Chorus - Downloadable Sounds - Wave Play and Record up to Eight Stereo Channels with Interactive 3-D Positioning - Game-compatible Synthesis - DirectSoundTM Static Buffer Support - 3-D Effect - Four-channel Surround (option) - Four-band Equalizer - Audio-in Effects (Reverb or Echo)
SAM9707
CODEC
DAC
Option
5
Functional Description
Figure 4. IC Architecture
Synthesis/DSP RISC DSP core includes: 512 x 32 Alg RAM 128 x 28 MA1 RAM 256 x 28 MA2 RAM 256 x 28 MB RAM 256 x 16 MX RAM 256 x 12 MY RAM 64 x 13 ML RAM
CODEC
P16 Processor 16-bit CISC Processor Core includes: 256 x 16 Data RAM 256 x 16 Boot ROM
MMU Memory Management Unit
ROM SRAM DRAM
I/O Functions including: Contol/Status MIDI UART Timers Codec Data I/F Host I/F FIFO Host I/F Burst
MIDI
ISA BUS
Synthesis/DSP Engine
The synthesis/DSP engine operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 micro-instructions known as "algorithms". Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical multimedia application will use half the capacity of the synthesis/DSP engine for synthesis, thus providing state-of-the-art 32-voice wavetable polyphony. The remaining processing power will be used for typical functions such as reverberation, chorus, direct sound, surround effect, equalizer, etc. Frequently accessed synthesis/DSP parameter data are stored into five banks of on-chip RAM memory. Sample data or delay lines, which are accessed relatively infrequently, are stored in external ROM, SRAM or DRAM memory. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to six simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 300 million operations per second (MOPS).
P16 Control Processor and I/O Functions
The P16 control processor is a general-purpose 16-bit CISC processor core that runs from external memory. A Boot/Macro ROM is included on-chip to accelerate commonly executed routines and to allow the use of RAM-only devices for the external memory. The P16 also includes 256 words of local RAM data memory. The P16 control processor writes to the parameter RAM blocks within the synthesis/DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the PC ISA interface and then controls the synthesis/DSP by writing into the parameter RAM
6
SAM9707
SAM9707
banks in the DSP core. Slowly changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the ISA PC interface, through specialized "intelligent" peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16. The ISA PC interface is implemented using three address lines (A2, A1, A0), a chip select signal, read-and-write strobes from the host and a 16-bit data bus (D0 - D15). The data bus can drive the PC bus directly (24 mA buffers). An external decoder (PAL) or plug & play IC is required to map the 12-bit I/O addresses and AEN from the PC into the three address lines and chip select from the SAM9707. The ISA PC interface supports a byte-wide primary I/O interface, a byte-wide auxiliary interface and a 16-bit port dedicated to burst transfers. The primary I/O interface is normally used to implement a Roland MPU-401 UART-mode compatible interface. It is specified by address A2A1A0 = 00X, address 000 being the data register and address 001 being the status/control registers. Besides the standard two status bits of the MPU401, two additional bits are provided to expand the MPU401 protocol. The auxiliary interface is allocated the address range A2A1A0 = 1XX. It is normally used to implement a gamecompatible interface. Address A2A1A0 = 010 specifies a 16-bit I/O port. It is mainly used for burst audio transfers to/from the PC using very efficient PC instructions such as REP OUTSW or REP INSW, which operate at maximum ISA bus bandwidth. This port may also be used for fast program or sound bank uploads.
Memory Management Unit (MMU)
The Memory Management Unit (MMU) block allows external ROM and/or RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows a single device (i.e., DRAM) to serve as sample memory storage/delay lines for the synthesis/DSP and as program storage/data memory for the P16 control processor.
7
Timings
All timing conditions: VCC = 5V, VC3 = 3.3V, TA = 25C, signals I/O READY, I/O CS16, D0 - D15 with 220 pull-up, 30 pF capacitance, signal IRQ with 470 pull-down, 30 pF capacitance, all other outputs except X2 and LFT load capacitance = 30 pF. All timings refer to tCK, which is the internal master clock period. The internal master clock frequency is four times the frequency at pin X1. Therefore, tCK = tXTAL/4. The sampling rate is given by 1/(tCK*1024). The maximum crystal frequency/clock frequency at X1 is 12.288 MHz (48 kHz sampling rate).
Crystal Frequency Selection Considerations
There is a trade-off between the crystal frequency and the support of widely available external DRAM/ROM components. Table 2 allows selection of the best fit for a given application.
Table 2. Crystal Frequency Selection Considerations
Sample Rate (kHz) 48 44.1 37.5 31.25 Crystal (MHz) 12.288 11.2896 9.60 8.00
tCK (ns)
20.35 22.14 26.04 31.25
ROM 1A (ns) 92 101 120 146
DRAM tRAC (ns) 72 80 95 116
DRAM tRC (ns) 92 101 120 146
Comment Maximum Frequency Recommended for Current Designs
Using a 11.2896 MHz crystal allows the use of widely available DRAMs (-6 type) with a cycle time (tRC) of 100 ns and an RAS access time of 60 ns, as well as widely available
ROMs with 100 ns access time, while providing state-ofthe-art 44.1 kHz sampling rate.
PC Host Interface Timing
Figure 5. PC Host Interface Timing Diagram A0 - A2 tAVCS CS RD SBHE I/O READY I/O CS16 tRDLDV D0 - D15
Note: D8 - 15 valid only if A2A1 = 10 and SBHE = 0.
tCSLRDL tRDLIORL tCSLIOCS
tPRD tPIOR
tRDHCSH
tCSHIOCS tIORHDV tDRH
8
SAM9707
SAM9707
Figure 6. PC Host Interface Write Cycle
A0-A2 tAVCS CS WR tWRLIORL I/O READY I/O CS16 tDWS D0-D15
Note: D8 - D15 valid only if A2A1 = 10.
tCSLWRL
tPWR tPIOR tIORHWRH
tWRHCSH
tCSLIOCS
tCSHIOCS
tDWH
Table 3. PC Host Interface Timing Parameters
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLVD tDRH tRDLIORL tPIOR tIORHDV tCSLIOCS tCSHIOCS tCSLRWRL tWRHCSH tPWR tWRLIORL tIORHWRH tDWS tDWH Notes: Parameter Address Valid to Chip Select Low Chip Select Low to RD or SBHE Low RD or SBHE High to CS High RD or SBHE Pulse Width Data Out Valid from RD or SBHE(2) Data Out Hold from RD or SBHE I/O Ready Low from RD or SBHE I/O Ready Pulse Width(3) I/O Ready Rising to Data Out Valid(3) I/O CS16 Low from CS Low
(4) (4) (3) (1)
Min 0 5 5 50
Typ
Max
Unit ns ns ns ns
20 5 0 10 10 128 0 0 0 5 5 50 20 20
ns ns ns
tCK
ns ns ns ns ns
I/O CS16 High from CS High
Chip Select Low to WR Low(3) WR High to CS High WR Pulse Width I/O Ready Low from WR Low
(3)
128 5 10
tCK
ns ns
I/O Ready High to WR High(3) Write Data Setup Time
Write Data Hold Time 0 ns 1. SBHE is normally not used (grounded). 2. When data is already loaded into internal SAM9707 output register. In this case I/O READY will stay high during the read cycle. 3. I/O READY will go low only if the data is not ready to be loaded into/read from internal SAM9707 register. 128 tCK corresponds to a single worst-case situation. At fCK = 11.2896 MHz, I/O READY is likely never to go low when using standard ISA bus timing. 4. I/O CS16 is asserted low by SAM9707 if A2A1 = 10 to indicate fast 16-bit ISA bus transfer to the PC.
9
External DRAM Timing
Figure 7. External DRAM Read Cycle
tRC tRAS RAS tRCD CAS DRA0DRA11 WOE tCAC WD0WD15 tRAC tOFF tASR tRAH tASC tCAS tCAH tCRP tRP
Figure 8. External DRAM Write Cycle (Early Write)
tRC tRAS RAS tRCD CAS DRA0DRA11 tWCS WWE tDS WD0WD15 tDH tWCH tASR tRAH tASC tCAS tCAH tCRP tRP
Figure 9. External DRAM Refresh Cycle (RAS Only)
tRC tRAS RAS tASR DRA0DRA11 tRAH tRP
counter
10
SAM9707
SAM9707
Table 4. External DRAM Timing Parameters
Symbol tRC tRAC tCAC tOFF tRP tRAS tCAS tRCD tCRP tASR tRAH tASC tCAH tWCS tWCH tDS tDH - Notes: Parameter Read/Write/Refresh Cycle Access Time from RAS Access Time from CAS CAS High to Output High-Z RAS Precharge Time RAS Pulse Width CAS Pulse Width RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Write Command Setup Time Write Command Hold Time Write Data Setup Time Write Data Hold Time 2 x tCK 3 x tCK - 5 3 x tCK - 5 Min 5 x tCK - 5 Typ Max 6 x tCK + 5 4 x tCK - 5 4 x tCK - 5 2 x tCK - 5 Unit ns ns ns ns ns ns ns
tCK - 5 tCK - 5 tCK - 5 tCK/2 tCK/2 - 5
3 x tCK
tCK + 5
ns ns ns ns ns ns
tCK
4 x tCK
ns ns ns ns
tCK
3 x tCK
Refresh Counter Average Period (12-bit Counter) 512 x tCK ns 1. The multiplexed CAS, RAS addressing can support memory DRAM chips up to 16 Mb as long as the number of row address lines and column address lines are identical. For example, device type 416C1200 is supported because it is a 1M x 16 organization with 10-bit row and 10-bit column. Device type 416C1000 is not supported because it is a 1M x 16 organization with 12-bit row and 8-bit column. 2. The signal WOE is normally not used for DRAM connection. It is represented only for reference purposes. 3. As RAS only counter refresh method is employed, several banks of DRAMs can be connected using simple external CAS decoding. Linear address lines (WAx) can be used to select between DRAM banks. For example, a 1M x 32 SIMM module may be connected as two 1M x 16 banks, with CAS0 and CAS1 selections issued from CAS and WA20. 4. During a whole DRAM cycle (from RAS low to CAS rising), WCS0 is asserted low. 5. The equivalence between multiplexed DRAM address lines (DRA0 to DRA11) and the corresponding linear addressing (WA0 to WA23) is as follows: DRA11 RAS Time CAS Time WA22 WA23 DRA10 WA20 WA21 DRA9 WA18 WA19 DRA8 WA8 WA17 DRA7 WA7 WA16 DRA6 WA6 WA15 DRA5 WA5 WA14 DRA4 WA4 WA13 DRA3 WA3 WA12 DRA2 WA2 WA11 DRA1 WA1 WA10 DRA0 WA0 WA9
6. To save DRAM power consumption, CAS and RAS are cycled only when necessary. Therefore, depending on firmware loaded, total board power consumption may increase with synthesis processing traffic.
11
External ROM Cycle Timing
Figure 10. External ROM Read Cycle
tRC WCS0 tCSOE WA0WA24 tPOE WOE tOE WD0WD15 tACE tDF
Table 5. External ROM Cycle Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF Parameter Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Access Time Output Enable Access Time Chip Select or WOE High to Input Data High-Z 5 x tCK - 5 3 x tCK - 5 0 2 x tCK - 5 Min 5 x tCK 2 x tCK - 5 3 x tCK Typ Max 6 x tCK 3 x tCK + 5 Unit ns ns ns ns ns ns
12
SAM9707
SAM9707
External RAM Timing
Figure 11. 16-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0WA24 tPOE WOE WWE tOE WD0WD15 tACE tDF
Figure 12. 16-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0WA24 WOE WWE tDW WD0WD15 tDH
tWP
Table 6. 16-bit SRAM Timing Parameters
Symbol tRC tCSOE tPOE tACE Parameter Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Access Time 5 x tCK - 5 Min 5 x tCK 2 x tCK - 5 3 x tCK Typ Max 6 x tCK 3 x tCK + 5 Unit ns ns ns ns
13
Table 6. 16-bit SRAM Timing Parameters
Symbol tOE tDF tWC tCSWE tWP tDW tDH Parameter Output Enable Access Time Chip Select or WOE High to Input Data High-Z Write Cycle Time Write Enable Low from CS or Address or WOE Write Pulse Width Data Out Setup Time Data Out Hold Time 4 x tCK - 10 10 Min 3 x tCK - 5 0 5 x tCK 2 x tCK - 10 4 x tCK 2 x tCK - 5 6 x tCK Typ Max Unit ns ns ns ns ns ns ns
Figure 13. 8-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0WA24 tPOE WOE WWE tACE RBS tOE WD0WD7 LOW tACH tDF HIGH tORB
14
SAM9707
SAM9707
Figure 14. 8-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0WA24 WOE WWE RBS tDW1 WD0WD7 tDH1 tDW2 HIGH tDH2
tWP tAS
tWP
LOW
Table 7. 8-bit SRAM Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tORB tACH tDF tWC tCSWE tWP tDW1 tDH1 tAS tDW2 tDH2 Parameter Word Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Low Byte Access Time Output Enable Low Byte Access Time Output Enable Low to Byte Select High Byte Select High Byte Access Time Chip Select or WOE High to Input Data High-Z Word Write Cycle Time First WWE Low from CS or Address or WOE Write (Low and High Byte) Pulse Width Data Out Low Byte Setup Time Data Out Low Byte Hold Time RBS High to Second Write Pulse Data Out High Byte Setup Time Data Out High Byte Hold Time 2 x tCK - 5 0 5 x tCK 2 x tCK - 10 1.5 x tCK - 5 1.5 x tCK - 10 0.5 x tCK + 10 0.5 x tCK - 5 2 x tCK - 10 10 2 x tCK - 5 6 x tCK 3 x tCK - 5 Min 5 x tCK 2 x tCK - 5 3 x tCK Typ Max 6 x tCK 3 x tCK + 5 Unit ns ns ns ns ns
tCK - 5 tCK
ns ns ns ns ns ns ns ns ns ns ns
15
Digital Audio Timing
Figure 15. Digital Audio Timing
tCW WSBD CLBD DABD0 DABD1 DAAD
tCW
tCLBD
tSOD
tSOD
Table 8. Digital Audio Timing Parameters
Symbol tWC tSOD tCLBD Parameter CLBD Rising to WSBD Change DABD Valid before/after CLBD Rising CLBD Cycle Time Min 8 x tCK - 10 8 x tCK - 10 16 x tCK Typ Max Unit ns ns ns
Figure 16. Digital Audio Frame Format
WSBD (I2S) WSBD Japanese CLBD
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
DABD0 DABD1 DAAD
MSB
LSB (16 bits)
LSB (20 bits) LSB (18 bits)
MSB
Notes:
1. Selection between I2S and Japanese format is a firmware option. 2. DAAD is 16 bits only. 3. When connected with codecs such as CS4216 or CS4218, D0 - D11 can be used to hold independent auxiliary information on left and right words. Refer to corresponding codec datasheets for details.
16
SAM9707
SAM9707
Reset and Power-down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take about 20 ms. The RESET signal is normally derived from the PC master reset. However, a typical RC/diode powerup network can also be used for some applications. After the low-to-high transition of RESET, the following occurs: * The synthesis/DSP enters an idle state, executing RAS only refresh cycles. * The RUN output is set to zero. * If BOOT is low, then P16 program execution starts from address 0100H in ROM space (WCS0 low). * If BOOT is high, then P16 program execution starts from address 0000H in internal bootstrap ROM space. The internal bootstrap expects to receive 256 words from the 16-bit burst transfer port, which will be stored from 0100H to 01FFH into the external DRAM space. The bootstrap then resumes control at address 0100H. If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power- down, PDWN has to be asserted high, then RESET applied.
Recommended Board Layout
Like all HCMOS high-integration ICs, the following simple rules of board layout are mandatory for reliable chip operation: * GND, VCC, VC3 distribution, decouplings All GND, VCC, VC3 pins should be connected. GND and VCC planes are strongly recommended below the SAM9707. The board GND and VCC distribution should be in grid form. If 3.3V supply is not available, then VC3 can be derived from VCC by two 1N4148 diodes in series. Recommended decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC3 requires a single 0.1 F decoupling close to the IC. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the SAM9707 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from SAM9707. * Buses Parallel layout from D0 - D15 and DRA0 - DRA11/WD0 WD15 should be avoided. The D0 - D15 bus is an asynchronous, high-transient, current-type bus. Even on short distances, it can induce pulses on DRA0 - DRA11/WD0 WD15, which can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D15 bus, which connects to the PC-ISA connector and to the SAM9707 GND. A ground plane should be implemented below the DRA0 DRA11/WD0 - WD15 bus, which connects to the DRAM SIMM grounds and to the SAM9707. * Analog section A specific AGND ground plane that connects by a single trace to the GND ground should be provided. No digital signals should cross the AGND plane. Refer to the codec vendor-recommended layout for correct implementation of the analog section.
17
Recommended Crystal Compensation and LFT Filter
X1 19 RESET 18 17 C4 22 pF C1 22 pF R1 100 C3 10 nF X1 X2
16 37 20
LFT BOOT PDWN
C2 2.2 nF
GND VCC
18
SAM9707
RUN
26
SAM9707
Absolute Maximum Ratings
Symbol Parameter/Condition Ambient Temperature (power applied) Storage Temperature Voltage on any pin (except X1) Voltage on X1 pin VCC VC3 Supply Voltage Supply Voltage Maximum IOL per I/O pin (except D[15:0], IRQ, I/O ready) Note: Maximum IOL, D[15:0], IRQ, I/O ready All voltages with respect to 0V, GND = 0V Min -40 -6.5 -0.5 -0.5 -0.5 -0.5 Typ Max +85 +150 VCC + 0.5 VC3 + 0.5 6.5 4.5 10 30 Unit C C V V V V mA mA
Recommended Operating Conditions
Symbol VCC VC3 TA Note: Parameter/Condition Supply Voltage Supply Voltage Operating Ambient Temperature
(1)
Min 3 3 0
Typ 3.3/5.0 3.3
Max 5.5 4.5 70
Unit V V C
1. When using 3.3V supply, care must be taken that voltage applied on pin does not exceed VCC + 0.5V.
DC Characteristics
TA = 25C, VC3 = 3.3V 10%
Symbol VIL VIH Parameter/Condition Low-level Input Voltage High-level Input Voltage Low-level Output Voltage D[15:0], IRQ, I/O ready: IOL = -24 mA others except LFT: IOL = -3.2 mA High-level Output Voltage D[15:0], IRQ, I/O ready: IOH =10 mA others except LFT: IOH = 0.8 mA Power Supply Current (crystal freq. = 12 MHz) Power-down Supply Current VCC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.8 4.5 70 25 70 90 35 100 Min -0.5 -0.5 2.3 3.3 Typ Max 1.0 1.7 3.8 5.5 0.45 0.45 Unit V V V V V V V V mA mA A
VOL
VOH
ICC
19
Mechanical Dimensions
Figure 17. 144-lead Thin Plastic Lead Quad Flat Pack
Table 9. Package Dimensions (in mm)
Dimension A A1 A2 D D1 E E1 L P B 0.17 Min 1.40 0.05 1.35 21.90 19.90 21.90 19.90 0.45 Typ 1.50 0.10 1.40 22.00 20.00 22.00 20.00 0.60 0.50 0.22 0.27 Max 1.60 0.15 1.45 22.10 20.10 22.10 20.10 0.75
20
SAM9707
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